'Today’s computers are horribly inefficient': How a US startup is going Apple's way — combining hardware and software to crack AI's big 99% power consumption problem

 Efficient Computer .
Efficient Computer .

Efficient Computer is living up to its name by creating what it describes as the most energy efficient programmable processor.

The startup emerged from stealth in March 2024 with $16m in seed financing led by Eclipse VC, and the claim to have built a completely new technology stack, from compiler to silicon, in a year.

The company’s approach is to create what it describes as a “general-purpose, post-von Neumann processor design that is easy to program and also extremely energy-efficient.”

Efficient structuring of memory

Brandon Lucia, Founder and CEO of Efficient Computer said, “Today’s computers are horribly inefficient. The dominant “von Neumann” processor design wastes 99% of energy. This inefficiency is, unfortunately, baked deeply into their design. In von Neumann processors, programs are expressed as a sequence of simple instructions, but running programs in a simple sequence is unacceptably slow. Improving performance requires complex hardware to find instructions that can safely run in parallel. Improving efficiency requires a fundamental rethinking of how we design computers.”

What that means in practice is instead of executing a series of instructions like von Neumann designs, its architecture “expresses programs as a 'circuit' of instructions that shows which instructions talk to each other.” This design, called Fabric processor architecture, has been implemented in the Monza test SoC.

Lucia was recently interviewed by eeNews Europe and explained in more detail what the company's approach involves. “What’s fundamentally different is the architecture was developed with compiler and software stack at the same time from research in Carnegie Mellon and we designed it with generality in mind,” he said. “We don’t need a register flow and we don’t need to instruction fetch every cycle. A subset of the tiles are also memory access tiles – that’s an efficient way of structuring the memory.”

The initial performance is 1.3 to 1.5TOPS/W, 500mW to 600mW for the chip, but that’s really just the beginning. “Looking to the future we have a roadmap to scale up the architecture as we are doing design space exploration. Early in 2025 we can hit 100GOPS at 200MHz and we think we can scale that 10 to 100x in performance with the same efficiency,” he said in the interview.

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